Adaptive logic circuits



Feb. 7, 1967 G. CLAPPER ADAPTIVE LOGIC CIRCUITS 2 Sheets-Sheet 1 FiledOct. 28 1963 (ABC) INVENTOR FIG. 10

X ENUNG L. CLAPPER BY 6m AGENT Feb. 7, 1967 L. CLAPPER ADAPTIVE LOGICCIRCUITS 2 Sheets-Sheet 2 Filed Oct. 28 1963 FIG. 1b

United States Patent 0 3,303,473 ADAPTIVE LOGIC CIRCUITS Genung L.Clapper, Vestal, N.Y., assignor to International Business MachinesCorporation, New York, N.Y., a corporation of New York Filed Oct. 28,1963, Ser. No. 319,317 11 Claims. (Cl. 340-1725) This invention relatesto logic circuits, and particularly to logic circuits which may betrained or adapted to changing input-output requirements.

Conventional logic circuits are arranged in accordance with well-knowndesign formulas and specifications so that, for a given set of inputconditions, a given set of output conditions will result. However, theinput-output relations are fixed by the circuit design and configurationand can only produce the input-output relations for which they wereoriginally designed.

Adaptive logic circuits are constructed and arranged so that a learningprocess is provided in which various input combinations are successivelyset up and desired output conditions are obtained therefrom. After thislearning or conditioning phase, the adaptive logic will continue toprovide outputs in accordance with the selected input conditions forwhich the circuits have become adapted. Thereafter, when desired, theadaptive logic circuits can be retrained to provide a new set ofresponses to new sets of selected input conditions.

Adaptive logic circuits as previously proposed have utilized deviceswhich vary in their response in accordance with variations inenvironmental conditions. That is, these devices are aifected by ambienttemperature, variation in power supply voltages, etc. Also, some ofthese devices are volatile in nature, and power supply interruptions cancause them to lose or change information stored therein.

Accordingly, it is a principal object of this invention to provide animproved adaptive logic circuit which is environmentally stable.

Another object of the invention is to provide an adaptive logic circuitwhich is non-volatile, retaining stored information in the absence ofpower.

A further object of the invention is to provide an adaptive logiccircuit utilizing a novel combination of transistors and a magneticcore.

Still another object of the invention is to provide an improved adaptivelogic circuit in which the stored information is transferred between atransistor latch circuit and a magnetic core, in such manner that apower failure will not result in either a loss of stored information ora change in the value of the stored information.

A further object of the invention is to provide an im proved adaptivelogic circuit in which a transistor latch circuit and a magnetic coreare combined to provide a non-volatile memory.

Still another object of the invention is to provide an improved adaptivelogic circuit in which an incandescent lamp is incorporated in thecircuit to function both as an indicating device and as an operatingcircuit element.

Briefly described, an adaptive logic circuit in accordance with thepresent invention comprises a magnetic core having a plurality ofwindings, a Z-transistor latch circuit and an incandescent indicatorlamp. A common input-output circuit connection is provided, and also aconditioning input circuit connection. The parts are arranged so that,when the input and conditioning circuits are each energized, the latchcircuit is turned on and the magnetic core is also set to a first stablecondition. With the circuit in this condition, input signals aretransmitted to the output. If the power supply fails or is turned oil,the enabled condition is retained by the ma g Patented Feb. 7, 1967netic core being in its set or first condition. When power is restored,the core is reset, or placed in a second stable condition. The fluxchange, which characterizes the conditioning of the core, turns thetransistor latch circuit on so that the circuit is restored to thecondition it was in when the power was removed.

This circuit also employs a conventional incandescent lamp which, inaddition to indicating the state of the logic circuit with which it isassociated, also functions as an integrating device due to the change inresistance of the filament as the temperature increases with time andcurrent.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

In the drawings:

FIGS. 1a and lb, placed side by side, are diagrammatic views of anadaptive logic system employing a preferred embodiment of the invention.

Referring to the drawings, a preferred embodiment of the invention isshown therein in diagrammatic form. The system comprising the inventionincludes a number of units which are similar in construction and areinterrelated in a manner to be subsequently described. For each of theunits which are similar in construction, only the detailed features ofone of the units is shown and de scribed, so that it will be obviousfrom the detailed description of one of the unitary elements how theremainder of the like elements are to be constructed.

The arrangement includes a plurality of input triggers, such as thetriggers designated AKT, BKT and CKT, only the detailed structure oftrigger AKT being shown. Associated with each of the input triggers isan input key such as the keys AK, BK and CK, and an indication lamp suchas the lamps AL, BL and CL. For the purpose of resetting the triggers,an input reset key IR is provided, which when operated will set thetriggers to their normal or off condition. The detailed structure ofeach of the triggers is similar to that shown within the dottedrectangle for trigger AKT. As shown, the trigger is of relativelyconventional construction, comprising a pair of emitter coupledtransistors, TRl and TR2, which are of the NPN junction type. The basesof transistors TRl and TR2 are connected to terminal l2 v. via resistorsR2 and R3, respectively. The bases of the two transistors arecross-coupled to the collectors of the other transistor of the pair viaresistors R4 and R5. For transistor TR2, a load resistor R6 is connectedbetween the collector of transistor TR2 and ground, while the load fortransistor TRl consists of the indicator lamp AL connected between thecollector of transistor TRl and ground. The base of transistor TRl isnormally connected to ground via a reversely biased diode D1 andresistor R7, but when input rest key IR is depressed, a 12 voltpotential is supplied via diode D1 to the base of the transistor TRl, toset the transistor in its olT condition, so that the trigger is set off.When it is desired to store one of the three possible inputs, input keyAK is depressed which connects the base of transistor TRI to ground viaresistor R8, which causes the trigger to reverse its conductive state,whereupon the lamp AL is lighted to indicate that trigger AKT has beenset on, and an output is supplied over the output line designated A. Theoutput line K does not have an output signal thereon at this time.

With the implementation of the circuitry as shown in the drawings, thepresence of a signal on a particular line, such as line A, is indicatedby this line standing at a value of approximately 2 volts, while theline on which no output signal is present; e.g., K, has a voltage ofapproximately 10 volts. With line K at 10 volts, it is apparent that a10-volt potential exists across the indication lamp AL; and this lampwould be lighted to indicate that the key trigger AKT controlled by thefirst key AK has been set on.

Each of the other two input triggers BKT and CKT operate in similarfashion. Since each of the triggers is independent in its operation fromthe other two, it can be seen that the three triggers can be set on oroff in all of the various combinations. Also, it is apparent from thedrawings that each of the triggers is provided with an output line andits complement; that is, A, K, B, 1?, C and 6. Thus, all the possiblevalues of the three input triggers are indicated by the outputs in thesix output lines therefrom. The outputs from the input triggers aresupplied in each of the various possible combinations out of the eightwhich are possible to circuits herein referred to as ANDemitter-followers designated by the reference characters &EF1 through&EF8. The structure of all of these circuits being similar, it is deemedsufiicient to describe only one in detail, that one being &EF1. As canbe seen, the inputs are supplied through three diodes, such as diodesD2, D3 and D4 connected to form an AND circuit including a resistor R10and which circuit is returned to the collector of a transistor TR14, viaa line designated as MR. The output of the AND circuit is connected tothe base of the transistor TR4, which has its collector connected toground through a resistor R12 and its emitter connected to -12 voltsthrough a resistor R13, the output therefrom being taken from theemitter in the usual fashion of an emittcnfollower circuit.

Each of the circuits &EF1 through &EF8 is connected to the appropriateones of the output lines from the three input triggers, in such mannerthat the outputs of these circuits represent the eight possiblecombinations which can exist for the input triggers. As oneillustration, &EF1 has its inputs connected to the A, Ti and 6 outputlines of the triggers AKT, BKT and CKT. The output from &EF1 accordinglyrepresents the condition A and E and a. The connections for each of theother seven circuits may be determined by noting the various connectionsof the input lines to the output lines of the triggers. The followingtable indicates the relations of these circuits to their outputs:

&EF3 ABC &EF5 ACE &EF6 BCK &EF7 ABC From the foregoing, it should beapparent that at all times there will be a signal on one of the outputlines of the circuits &EF1 through &EF8, which signal represents thestate of the input triggers AKT, BKT and CKT.

The outputs from &EF1 through &EF8 are the outputs of the triggers AKT,BKT and CKT in all of their combinations. Since there are threetriggers, each having two states, there are 2 or eight combinations.These combinations are shown by the letters in parentheses on the outputlines from &EF1 through &EF8 as given in the following table:

The outputs from StEFl through &EF8 are supplied to a plurality ofadaptive memory units, designated by the reference characters AMIthrough AM16. In the present case there are 16 memory units since thereare eight possible input combinations and two output conditions to beprovided for each of the eight input conditions. Accordingly, sixteenadaptive memory units are required. Each of the units is similar to thatshown in detail in the dotted rectangle designated by referencecharacter AMI and the description of this one unit will suffice for all.The unit includes a transistor latch including two transistors TR6 andTRS, and a magnetic core designated by the reference character MC. CoreMC has three windings thereon designated by the reference characters 5,7 and 9, all wound in similar sense. The winding 5 is connected via aresistor R15 to the collector of transistor TR8, the other terminal ofwinding 5 being connected to ground. One terminal of winding 7 isconnected to ground and the other is connected through a resistor R17 toa memory setting circuit including the key switch designated byreference characters M SET, which when closed connects the windings 7 ofall of the cores in the adaptive memory units to ground via a capacitorQ1, which provides a resetting action to be subsequently described. Thewinding 9 of core MC has one terminal thereof connected to the emitterof transistor TR6, the other end of the winding being connected to theemitter of transistor TRS via a diode D7, this terminal of the windingalso being connected to one terminal of an indicator lamp designated bythe reference character AM1L, the lamp circuit being completed to thepower terminal 12 v. The collector of transistor TR6 is connected to thebase of transistor TRS and also through a resistor R19 and a normallyclosed resetting key designated by the reference characters M RESET toground. The base of transistor TR6 i connected via a resistor R21 to anadjustable source of biasing potential designated by referencecharacters ETH. The value of this voltage is chosen to provide asuitable threshold operating voltage for the adaptive memory unit. Oneof the inputs to each of the memory units, as previously mentioned, isfrom the AND emitter followers &EF1 through &EF8, while the other inputis supplied from one of a plurality of conditioning units designated bythe reference characters CUl through CU4. The input from the AND emitterfollowers is via a resistor R23, and a diode D8 to the circuit connectedto the left-l1and terminal of winding 9 of the core MC. The input fromthe conditioning unit is connected directly to the junction betweendiode D8 and the winding 9 of core MC. The output from each of theadaptive memory units is taken from the junction between the resistorR23 and the diode D8 and these outputs, of which there are 16, aresupplied to the appropriate one of two output mixer units designated bythe reference characters XOM and YOM, the structure of which will besubsequently described in detail. The combination of the parts in eachof the adaptive memory units comprises a novel combination including alatchtype transistor circuit which is arranged to cooperate with themagnetic core in such fashion that loss of power will not cause a lossof the information or conditions stored in the latch circuit.Conditioning of the latch circuit will set the core in such manner that,should the power supply to the unit be turned off for any reason,restoration of the power and operation of the setting switches willcause the magnetic core to reset the transistor latch circuit to itsprevious condition.

In operation, with power on and the M RESET switch closed, thetransistor TR6 has its collector connected to ground through resistorR19. The threshold voltage ETH is set to some suitable value in thepower supply, not shown, such as, for example, -9 volts. Current flowsthrough transistor TR6, through the winding 9 of the core MC and throughlamp AMlL to the 12 v. terminal. The value of resistor R19 issufficiently high that the current flow through lamp AMIL isinsufficient to cause it to glow visibly. Also, the value of the currentis insufiicient to cause any change in the core MC.

Consider now the operation of the adaptive memory units under thecondition where an input is supplied to the adaptive memory unit from anappropriate AND emitterfollower, but no conditioning input is suppliedthereto. In this case, either the conditioning keys XCK and YCK are openor the conditioning switch CON is not operated. The conditioning unitsin the illustrative embodiment are designated by the referencecharacters CU1, CU2, CU3 and CU4. All of these units are identical instructure, and the detailed circuitry is shown for one. As shown in thedotted rectangle designated by the reference character CU4, theconditioning unit comprises a plurality of diodes such as D9, D11, D13and D15, each connected to a 12 volt source via an individual resistorsuch as R25, R27, R29 and R31 and a common dropping resistor R33. Thejunction between the individual load resistors and the common resistor iconnected via a key such as YCK to a conditioning switch CON, which whenin its on position connects the keys YCK and XCK to ground, and alsocompletes a circuit through a conditioning indication lamp CONL, viaresistor R41 to a 12 volt source, so that an indication is provided whenthe system is in it conditioning state. Since there are sixteen adaptivememory units, and two output conditions to be provided, it can be seenthat the conditioning units CU1 and CU2 are arranged to be conditionedby operation of the first conditioning key XCK, and connections fromunits CU1 and CU2 are established to the adaptive units AMl through AM8.Conditioning units CU3 and CU4 have circuits connected to the adaptivememory units AM9 through AM16, the connections between units CU4 andadaptive memory units AM13 through AM16 being shown in detail, while theremainder of the circuits are eliminated for the sake of clarity.

Now from the preceding description of the conditioning units CU4, it canbe seen that the connection from conditioning unit 1 to adaptive memoryunit 1, designated by the reference character CU10 will, at this time,have a potential of 12 volts thereon.

The value of resistor R23 is so chosen with respect to the resistance ofbulb AMlL so that the voltage at the emitter of transistor TR6 does notgo as high as the threshold voltage ETH, and therefore transistor TR6remains in conducting condition and transistor TR8 remains cut off.Under these circumstances, the voltage on the output line which isconnected at the junction of resistor R23 and diode D8, and for adaptivememory unit AMI is designated by the reference character AM10, has itsoutput voltage limited to approximately 10 volts. This voltage will notoperate the associated output mixing device, later to be described,which requires approximately 6 volts for its operation.

If the conditioning switch CON is now turned on so that ground iseffectively supplied to the conditioning keys or switches XCK and YCK,operation of the switch XCK will, via the conditioning unit CU1, apply apotential via the line CUltl to the adaptive memory unit AMl such thatadditional current will now flow through the lamp AMlL, the parts beingproportioned and arranged so that there is essentially double the amountof current flowing through the bulb. At this time the voltage at theemitter of transistor TR6 will rise by virtue of the increased currentflow through the lamp AMlL, increasing the voltage drop thereacross,with a concomitant increase with is transmitted by winding 9 to theemitter of transistor TR6. The emitter of transistor TR6 rises about thepotential ETH, which thereby cuts off conduction in transistor TR6 sothat the collector voltage of this transistor rises. As a result, thevoltage at the emitter of transistor TR8 will also rise; and with theconnection between the emitter of transistor TR8 via diode D7 to theemitter of transistor TR6, the emitter of TR6 will have its voltagemaintained sufiiciently high to maintain TR6 cut off, even if the inputand the conditioning pulses are now removed.

With the adaptive memory circuit in this condition, if an in ut signalis now applied via the line A, it is not attenuated and full output isfurnished via the output line AM10 to the output mixer unit XOM.

The output mixers XOM and YOM are identical in construction andoperation and, accordingly, only one of the two, YOM, need be describedin detail. Each of the output mixer units has as inputs thereto eight ofthe output lines from a selected eight of the adaptive memory units, theoutput unit XOM having inputs from adaptive memory units AMI throughAM8, while unit YOM receives the output lines from adaptive memory unitsAM9 through AM16. As shown in the dotted rectangle designated YOM, eachof these lines is supplied to a respective input diode in a conventionaldiode mixing circuit, such as that including the diodes D17, D19, D21,D23, D25, D27, D29 and D31. These have a common load resistor R34 whichis connected from the junction between the diodes to the negative sourceof potential 12 v. The output from this diode mixer circuit is suppliedvia resistor R35 to the base of an NPN transistor TRIO, the emitter ofwhich is connected to negative potential 6 v., while the collector isconnected through load resistances R36 and R38 to ground, and also tothe base of PNP transistor TR12 via R36. The emitter of transistor TR12is connected to ground through a diode D33, while the collector isconnected by resistor R39 and an indicating lamp YL to 12 v. A resistorR37 is connected in shunt from the emitter of transistor TR12 to thelamp YL. In operation, the lamp YL is normally dark since insuflicientcurrent flows therethrough to cause the lamp to be illuminated, but whenany one or more of the input lines has a signal supplied thereto whichraises the potential to approximately 6 V., the transistors TRIO andTR12 will supply sufficient energy through lamp YL to illuminate thelamp, thereby indicating an output on one of the eight associatedadaptive memory unit output lines.

Accordingly, under the last-described conditions for the adaptive memoryunit AMI, with a signal present on the output line AMll], the indicatinglamp XL associated with output mixer XOM would be illuminated.

Now considering the operation of the adaptive memory units with respectto the cooperation of the transistor latch circuit and the magneticcore, it will first be assumed that the latch circuit has been placed inits on condition in a manner previously described. When the latch isturned on, TR8 is conducting and the accompanying How of current throughwinding 5 of magnetic core C will cause the core to be magnetized in adirection which may be considered its on state.

Then it the power is removed from the circuit, the core will not changefrom its first magnetized state, even though the flow of current isinterrupted through winding 5, because of the stable remanentcharacteristics of the core as is well known in magnetic core storageart. If the power is then turned back on, the M SET key is operated, atwhich time the charge on capacitor Q1 will be discharged through the MSET switch, through resistor R17 and winding 7 on the core MC to ground.This current pulse will reset the magnetic core MC to its otf state, andwill cause a voltage impulse to be induced in winding 9 of the corewhich is of a polarity which causes the emitter of transistor TR6 torise and will cut off conduction in transistor TR6. Transistor TR8 willnow conduct and cause transistor TR6 to remain cut off by holding theemitter thereof at a high level. The How of current in winding 5 at thistime will again set the core MC to its first or on state.

If it is now desired to destroy information in the adaptive memory unitAMI, the switch M RESET is operated at the same time as the switch M SETis operated. Under these circumstances, the core MC is reset by theenergy supplied from capacitor Q1, but even though the emitter voltageof transistor TR6 rises as previously described, the collector of thistransistor cannot rise because the connection to ground is interruptedat the contact of the switch M RESET. Under these circumstances, thebase of transistor TR8 does not rise and therefore, transistor TR6 isnot maintained in its non-conducting condition. Thus, the latch circuitdoes not come on even after the M RESET switch is released and theadaptive memory unit returns to its initial or off state.

The circuit for supplying charging energy to the resetting capacitor Qlincludes a pair of complementary transistors TR14 and TR16, the PNPtransistor TR14 having its emitter connected through a diode D35 and thecontact of the M RESET key to ground with the base of transistor T R14connected to the collector load resistors R41 and R43, which areconnected in series between the collector of TR16 to ground. Thecollector of transistor TR14 is connected to a junction point fromwhence resistor R45 establishes a connection to the base of transistorTR16, the diode D37 is included in a connection to the capacitor Q1, andresistor R47 is connected from the junction to a negative source ofpotential 12 v. To this same junction point is connected the common lineMR which supplies energy to each of the load resistors in the ANDemittenfollowers shown in FIG. la. The pair of transistors acts as alatch which serves to put a suitable back-biasing voltage on thecharging diode D37, so that the capacitor Q1 is decoupled from thecharging source when the latch is on. When power is first applied, orfollowing operation of the M RESET key, the latch circuit comprisingtransistors TR14 and TR16 is off; that is, both transistors arenonconducting. In this state, a charg ing path is provided for capacitorQ1 to the l?. v. potential via the diode D37 and the resistor R47. Whenthe M SET key is operated, capacitor Q1 discharges through the corewindings and the potential at the anode of diode D37 rises towardground. As current fiows in the diode D37, the voltage at the junctionof resistors R47, R45 and the collector of transistor TR14 also rises.When the voltage at the junction reaches approximately 6 volts, the biason the transistor TR16 is removed and the voltage at the collector ofthis transistor drops to approximately 6 volts. This turns on transistorTR14 raising the voltage at the junction of its collector, and thecircuit is accordingly latched up. As the voltage rises at the junction,the charging path for the capacitor Q1 is decoupled by the back-biasingof diode D37, and the back resistance of this diode is normally enoughto insure that the capacitor is fully discharged so that the M SET keyis ineffective. At any time thereafter, operation of the M RESET key orremoval of the power source will cause the transistors TR14 and TR16 todrop out of conduction and place the latch circuit in its off condition,which permits another single shot of energy to thereafter be supplied tothe core setting circuits by operation of the M SET key.

Under normal operating conditions, the M SET key having been operated,the latch circuit is in its on condition with the transistors TR14 andTR16 conducting, so that the junction point to which the line MRconnected is relatively high in potential, and thus all of the input ANDcircuits in the AND emitter-followers &EF1 through &EF8 are enabled, sothat inputs may be supplied therefrom to the adaptive memory units.Thus, the interlock circuit serves to (1) prevent more than one pulse ofenergy being supplied to the core setting circuits from capacitor Q1 foreach operation of switch M SET and (2) disable the inputs so that no newinput conditions can be registered unless and until the proper sequenceof operations of the M SET and M RESET keys is employed. This insuresthat any time that the M RESET is operated to restore the transistorlatch circuit portions of the adaptive memories, the M SET key mustthereafter be operated in order to transfer any information stored inthe magnetic cores of the adaptive memories to the latch circuits, sothat all information in the cores is placed in the latches when theadaptive memories are in their normally operative state. Until the M SETkey is operated to turn on the interlock latch, new inputs are renderedineffective by disabling the input circuitry.

The operation of the system as a whole will now be described, since eachof the component circuit arrangements has been explained in detailhereinbefore. To first utilize this system, the various sources ofpotential will be energized by energizing the power supply whichsupplies the apparatus, the details of this supply not being shown ordescribed since it forms no part of the invention. With power suppliedto the circuits, the M SET key is now operated so that any storedinformation which is in the magnetic cores of the adaptive memory unitswill be supplied to the transistor latches, and the transistor latcheswill be set on and such condition will be indicated by illumination ofthe associated indicator light, such as the lamp AMIL associated withadaptive memory unit AMI.

If it is desired that new information be entered, the M RESET key shouldthen be operated and maintained in an operated or open state whilesimultaneously closing the M SET key which will cause the storedinformation to be erased as was previously described in the detaileddescription of the operation of the adaptive memory units. The erasureof the stored information can be checked by re leasing the M RESET keyand thereafter pressing the M SET key. At this time, each of theindicator lamps associated with the adaptive memory units should remainoff, indicating that all the adaptive memory units have been cleared ofinformation and are ready for conditioning.

For the conditioning operation, the conditioning switch CON is placed inits on position as shown in the drawings, at which time the conditionindicating lamp CONL will be lighted and the ground connection will beestablished to the two output condition keys XCK and YCK. Theseconditioning keys should not be operated until the input register hasbeen cleared by operation of the input register reset key IR, FIGURE 1a.The desired input and output relations having been set up in a truthtable indicating the binary values of the inputs a, b and c, and thedesired outputs x and these values may be entered into the adaptivememory units one by one. In doing this, the input keys AK, BK and CK areoperated as required to indicate the particular input conditions, andthereafter the output condition keys XCK and YCK are operated toindicate the desired output conditions. After each set of values isentered the input register is reset by operation of the register resetkey IR and the next set of values is entered into the inputs followed byconditioning by operation of the output condition keys. Since theadaptive memory units set up in connection with the various input andoutput conditions each have an individual indicator lamp associatedtherewith, these conditions can be checked by noting the indicationlamps which are on, indicating that a particular adaptive memory unit isactive.

After all of the truth table values have been entered into the system,the conditioning switch is turned off, so that further conditioningcannot take place. At this time, all of the adaptive memory units whichhave been properly conditioned during the conditioning process will beon and, as previously explained, will alford a low impedance pathbetween the input thereto and the output to the output mixer unitassociated with the particular adaptive memory unit. Thereafter, forparticular input conditions as determined by operations of the keys AK,BK and CK, particular ones of the adaptive memory units will supplyoutputs to the output mixer units XOM or YOM, or both, to thereby lighteither the lamp XL or the lamy YL, or both of these lamps.

To set up a new combination of conditions in the adaptive memory units,the preceding operations may be repeated, starting with destruction ofthe information stored in the adaptive memory units by operation of theM SET and M RESET keys.

As was previously pointed out, with a particular combination of adaptivememory units activated as described above, if the power is turned offand then turned on again, the information which in the interim is storedin the magnetic cores associated with each of the adaptive memory unitswill be returned to the transistor latch circuit portion of the adaptivememory unit, so that the adaptive memory units will be again set to therequired combinations. Thus, it will be apparent that, once havingconditioned the adaptive memory units for a particular set of input andoutput conditions, only deliberate action can destroy the particularlogical combination obtained thereby, since the system is not affectedby temporary or sustained loss of power, either accidentally ordeliberately.

From the foregoing, it will be apparent that the present inventionprovides a novel and improved form of adaptive memory unit, which may becombined with input and output units to provide an adaptive logic systemwhich is stable in its operation and is non-volatile in that loss ofpower accidentally or otherwise does not cause the adaptive logic systemto change the logic combination for which it has been set.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:

1. An adaptive logic system comprising, in combination,

a plurality of input circuits, each capable of supplying input signalstherefrom;

a plurality of output circuits, each requiring the supply thereto ofoutput signals to render said output circuits effective;

a plurality of conditioning circuits, each capable of supplyingconditioning signals therefrom; and

a plurality of adaptive memory units, each of said adaptive memory unitshaving an input connected to an associated one of said input circuits,an output connected to an associated one of said output circuits, and aconditioning input connected to one of said conditioning circuits, andarranged to provide an output to said output circuit when and only whenan input is provided to said input circuit, following the supply to saidunit of an input from said input circiut and a conditioning signal fromsaid conditioning circuit.

2. An adaptive logic system comprising, in combination,

a plurality of adaptive logic units, each unit being capable of assuminga first or a second stable state, said first state being a referencestate, each of said units being established in said second state onlyupon the supply thereto of an input signal and a conditioning signal,each of said units supplying an output signal upon supply thereto of aninput signal when and only when said unit is in said second state;

a plurality of input signal lines;

transformation means for transforming each possible combination of saidinputs into a transformed input signal, each of said transformed inputsignals being supplied to an associated adaptive logic unit;

at least one conditioning signal source;

means for supplying conditioning signals from said source to saidadaptive logic units; and

output signal means connected to said adaptive logic units and governedby the output signals from said adaptive logic units.

3. An adaptive logic system comprising, in combination,

a plurality of adaptive logic units, each unit being capable of assuminga first or a second stable state, each of said units being establishedin said second state only upon the supply thereto of an input signal anda conditioning signal, each of said units supplying an output signalupon supply thereto of an input signal when and only when said unit isin said second state;

a plurality of input signal lines;

transformation means for transforming each parallel combination of saidinputs into a transformed input signal, each of said transformed inputsignals being supplied to an associated adaptive logic unit;

a plurality of conditioning signal lines, one for each group of adaptivelogic units defined by said transformed input signals, said conditioningsignal lines being connected to each of the adaptive logic units in theassociated group; and

output signal means, one for each group of adaptive logic units,connected to said adaptive logic units to indicate the state of theassociated group of adaptive logic units.

4. An adaptive logic system comprising, in combination,

a plurality of input lines, n in number;

a plurality of output lines, m in number;

transformation means connected to said input lines and providing aplurality of 2" transformed input lines representing each possiblecombination of input lines;

a plurality of conditioning signal lines, m in number;

and

a plurality m(2") of adaptive logic units, each unit being capable ofassuming a first or a second stable state, said first state being areference state, each of said units being established in said secondstate only upon the supply thereto of an input signal from an associatedone of said transformed input lines and an associated one of saidconditioning signal lines, each of said units providing an output signalto an associated one of said output lines upon supply thereto of aninput signal on said associated transformed input line when and onlywhen said unit is in said second state.

5. An adaptive logic system as claimed in claim 4 in which the signalsare binary valued.

6. An adaptive logic system comprising, in combination,

a plurality of input lines, 22 in number;

a plurality of input registers, n in number, one for each of said inputlines;

a reset line common to all of said registers;

a first and a second register output line for each of said registers;

said registers being effective when reset by a signal supplied from saidreset line to provide a first output on said first register output line,said registers being settable by signals supplied thereto on said inputlines to provide a second output on said register output line;

transformation means connected to said register output lines forproviding a plurality of transformed output signals equal in number to2;

a plurality of conditioning signal lines, m in number;

a plurality of logic output lines, n in number; and

a plurality of adaptive logic units, equal in number to 111(2), eachunit being capable of assuming a first or a second stable state, saidfirst state being a reference state, each of said units beingestablished in said second state only upon the supply thereto of aninput signal from an associated one of said transformed input lines andan associated one of said conditioning signal lines, each of said unitsproviding an output signal to an associated one of said output linesupon supply thereto of an input signal on said associated transformedinput line when and only when said unit is in said second state.

7. An adaptive logic unit comprising, in combination,

a magnetic core having a plurality of windings thereon and having afirst and a second remanent flux state;

a transistor latch circuit comprising a first and a second transistor,with the collector of said first transistor coupled to the base of thesecond transistor;

circuit means including a first winding of said core for coupling theemitters of said first and second transistors;

means for supplying a threshold voltage to the base of said firsttransistor;

means for supplying operating voltages to the emitter and collector ofsaid first transistor so that said first transistor is normallyconducting;

means including a second winding on said core for supplying an operatingvoltage to the collector of said second transistor;

means for supplying an input signal to the emitter of said firsttransistor effective to render the first transistor nonconducting andsaid second transistor conducting, the current flow through the windingof said core connected to the collector of said second transistor beingeffective to set said core in its second state;

an output circuit for said logic unit; and

means responsive to conduction of said second transistor to conditionsaid output circuit to provide an output therefrom in response to aninput signal supply to said emitter of said first transistor.

8. An adaptive logic unit comprising, in combination,

a magnetic core having two stable remanent flux states;

a first, a second and a third winding on said core;

a first and a second transistor;

said first transistor having its collector and base connected to sourcesof operating potential and having its collector connected to the base ofsaid second transistor;

said second transistor having its collector connected in series withsaid first winding to a source of operating potential;

input and output circuit means connected to the emitter of said secondtransistor in series with said second winding to the emitter of saidfirst transistor;

means for supplying energy to said third Winding to establish said corein a first one of said two stable remanent flux states;

the parts being proportioned and arranged so that the supply of asuitable signal to said input and output circuit means establishes saidtransistors in a selected conductive state and causes said core to beset to the second one of said two stable remanent fiux states; and

the sense of said windings being selected so that the resetting of saidcore to said first state induces energy in said second winding effectiveto cause said transistors to acquire said selected conductive state.

9. An adaptive logic unit as claimed in claim 8 in which said input andoutput circuit means includes a non-linear impedance connected betweensaid circuit means and a source of operating potential to form acombined current summation and integrating means.

10. An adaptive logic unit as claimed in claim 9 in which saidnon-linear impedance is an incandescent lamp which is supplied withsufficient current to glow visibly only when said transistors are insaid selected conductive condition.

11. An adaptive logic unit comprising, in combination,

a magnetic core having a first and a second stable remanent flux state;

a first, a second and a third winding on said core;

a semiconductor latch circuit having a first and a second stableconductive state; means for supplying input signals to said latchcircuit effective to cause its transference from said first conductivestate to said second conductive state;

circuit means connecting said first winding to said latch circuit andeffective to set said core in its second state when said latch circuitis in said second conductive state;

circuit means connecting said second winding to said latch circuit andeffective to turn said latch circuit on when said core is returned fromits second state to its first state; and

reset circuit means connected to said third winding and effective totransfer said core from said second to said first state.

References Cited by the Examiner UNITED STATES PATENTS 10/1963 Kamentsky340-1725 8/1965 Anderson et al. 307-88

1. AN ADAPTIVE LOGIC SYSTEM COMPRISING, IN COMBINATION, A PLURALITY OFINPUT CIRCUITS, EACH CAPABLE OF SUPPLYING INPUT SIGNALS THEREFROM; APLURALITY OF OUTPUT CIRCUITS, EACH REQUIRING THE SUPPLY THERETO OFOUTPUT SIGNALS TO RENDER SAID OUTPUT CIRCUITS EFFECTIVE; A PLURALITY OFCONDITIONING CIRCUITS, EACH CAPABLE OF SUPPLYING CONDITIONING SIGNALSTHEREFROM; AND A PLURALITY OF ADAPTIVE MEMORY UNITS, EACH OF SAIDADAPTIVE MEMORY UNITS HAVING AN INPUT CONNECTED TO AN ASSOCIATED ONE OFSAID INPUT CIRCUITS, AN OUTPUT CONNECTED TO AN ASSOCIATED ONE OF SAIDOUTPUT CIRCUITS, AND A CONDITIONING INPUT CONNECTED TO ONE OF SAIDCONDITIONING CIRCUITS, AND ARRANGED TO PROVIDE AN OUTPUT TO SAID OUTPUTCIRCUIT WHEN AND ONLY WHEN AN INPUT IS PROVIDED TO SAID INPUT CIRCUIT,FOLLOWING THE SUPPLY TO SAID UNIT OF AN INPUT FROM SAID INPUT CIRCUITAND A CONDITIONING SIGNAL FROM SAID CONDITIONING CIRCUIT.